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10th IEEE INTERNATIONAL TEST CONFERENCE INDIA 2026

JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU

Call for Papers

Celebrating its 10th edition, the IEEE International Test Conference India (ITC India) is the premier conference dedicated to testing of electronic devices, circuits, and systems. ITC India 2026 invites researchers, developers, and practitioners from academia and industry to submit original, unpublished work on all aspects of VLSI test, reliability, yield, and quality for current and emerging semiconductor technologies.

We seek high-quality unpublished submissions for papers (4-6 pages) and posters (1-6 pages) covering the theoretical, practical, and experimental aspects of VLSI testing.

Submission Format

  • Full Papers: 4-6 pages following IEEE standard two-column format
  • Posters: 1-6 pages following IEEE standard two-column format
  • All submissions must adhere to IEEE conference template guidelines

Review Process

  • All submissions undergo a rigorous double-blind peer review process
  • Multiple expert reviewers evaluate each submission for technical quality, originality, and relevance
  • Authors must ensure anonymity in their submissions

Submission Guidelines

  • Submissions simultaneously under review or accepted by another conference, symposium or journal, will be summarily rejected
  • Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore's scope and quality requirements
  • For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India web site at https://itctestweekindia.org or email the program chair at ITC-India-2026-TPC@easychair.org
  • An abstract of 100 words or less must be entered online on the submission site
  • An electronic copy of a complete paper up to 6 pages, double-columned in IEEE Format, A4 size (https://www.ieee.org/conferences/publishing/templates.html) to be submitted through EasyChair (https://easychair.org/conferences/?conf=itcindia2026)
  • Your submission must not include information that serves to identify the authors of the manuscript, such as name(s) or affiliation(s) of the author(s), anywhere in the manuscript, abstract, or in the embedded PDF data. References and bibliographic citations to the author(s) own published works or affiliations should be made in the third person
  • A submission of 1-3 pages will be reviewed as a poster submission. A submission of 4-6 pages may be accepted as a paper or poster depending on the reviewer feedback

Conference Tracks & Suggested Topics

(not limited to)

Heterogeneous Integration, Chiplets & 2.5D/3D Test

  • DFT for chiplets and die-to-die links
  • KGD qualification
  • 2.5D/3D interconnect test
  • 2.5D/3D test standards

AI/ML-Driven Test, Adaptive Quality & Outlier Management

  • Adaptive test frameworks
  • Outlier detection, drift monitoring, false-positive control
  • Agentic AI applications in DFT

Automotive, Functional Safety & Mission-Profile Testing

  • ISO 26262 compliant DFT
  • Latent defect screening and stress-based tests
  • In-system safety monitors and self-test (LBIST/MBIST in-field)

Analog, RF & Mixed-Signal Test for 5G/6G, Power & Sensing

  • High-frequency test methods (mmWave/THz)
  • Power/PMIC test
  • Sensor, interface test (MEMS, precision analog)
  • Jitter, High-Speed I/O and RF Test

Memory & Storage Test: HBM, DDR/LPDDR, NVM

  • HBM stack test
  • DRAM/LPDDR test for pattern-sensitive faults
  • Memory test and repair
  • NVM test for endurance, retention, disturb mechanisms

Hardware Security, Trust & Secure Test Access

  • Secure JTAG/IJTAG access control and authentication
  • Confidential test content and data protection
  • Side-channel aware test
  • Hardware trojan detection
  • PUF characterization and reliability

DFT, ATPG, Diagnosis & Test Standards

  • Advancements in DFT and ATPG
  • Advanced fault models and defect based testing
  • Test standards
  • DFM and test diagnosis

System-Level Test (SLT), Reliability and Silicon Lifecycle Management

  • SLT architectures
  • Field Monitoring, test and debug
  • End-to-End data analysis
  • Silent data corruption

Test Economics, Operations & Sustainability

  • ATE/Probe card design
  • Test time optimization and content prioritization
  • Yield analysis and optimization
  • Silicon debug and test escape analysis
  • OSAT collaboration and vendor-neutral interfaces

Testing for Emerging Applications

  • Quantum device testing
  • Testing high speed optics/photonics
  • Neuromorphic computing

Important Dates

Abstract Submission Deadline

CLOSED

Paper Submission Deadline

CLOSED

Author Notification

10th May, 2026

Camera-ready Paper and IEEE Copyright Transfer Due

31st May 2026

SUBMIT PAPER

Need Help?

For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India web site or email us.

Website:itctestweekindia.org

Program Chair Email:ITC-India-2026-TPC@easychair.org

We look forward to your contributions to ITC India 2026!