10th IEEE INTERNATIONAL TEST CONFERENCE INDIA 2026

JUL 19-21, 2026 | BENGALURU, INDIA

Call for Tutorials

Submission Guidelines

  • A tutorial proposal needs to be submitted in template available on ITC India website
  • Submission link: https://easychair.org/my/conference?conf=itcindia2026
  • The following details are mandatory:
    • Tutorial title
    • Tutorial abstract
    • Topics and subtopics to be covered, and the approximate time devoted to each topic
    • The targeted audience and prerequisites
    • Preferred tutorial duration: 3 hours (for full tutorials) or 1.5 hours (for short tutorials)
    • Name, affiliation, bio of each author
  • Proposals will undergo a panel review process
  • All presenters listed in the tutorial proposal must be available for tutorial presentation
  • Consent should be obtained from all the presenters and all organizations involved in presenting the material before making the tutorial proposal
  • If proposal is accepted, final presentation must be shared by final manuscript due date for review
  • Accepted tutorial abstracts will be published in conference proceedings

Call for Submission

International Test Conference is the world’s premier venue dedicated to the electronic test of devices, boards and systems—covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process and design improvement. At ITC India, design, test, and yield professionals can confront challenges faced by the industry, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. This ITC India conference will be focusing on Test development in India, but the submissions may not be limited to topics related to this region. Topics related to design and test development across multi geographical regions will be of special interest.

Authors are invited to submit original, high quality, practical and industry best practices as Tutorials describing recent work in the field of test and design.

Topics of Interest

Include (not limited to):

3D/2.5D IC and Chiplet Testing
Adaptive Test in Practice
ATE/Probe Card Design
Automotive Reliability and Testing
Advances in Boundary Scan
Silicon Bring Up
Defect-Oriented Testing
DFM and Test Diagnosis
Economics of Test
Embedded BIST & DFT
Emerging Defect Mechanisms
Hardware Security and Trust
High-Speed Interface Testing
IoT Testing
Known-Good-Die testing
Low-Power Testing Techniques
Machine learning applications in DFT
Memory Test and Repair
MEMS Testing
Mixed-Signal and Analog Test
New Technologies and Test
On-Chip Test Compression
Online Test
Pre- and Post- Silicon Validation
Quantum Computing Hardware Testing
Reliability and Resilience
Scan Based Test
Security and trust in DFT
SoC/SiP/NoC Test
Silicon Debug and diagnosis
Jitter, RF Test
Simulation and Test
System Test
Test-to-Design Feedback
Test Data Analytics, Big Data in Testing
Test Escape Analysis
Test Flow Optimizations
Test Generation and Validation
Test Resource Partitioning
Test Standards and best practices in DFT
Test Time Analysis and Reduction
Testing and Validation of AI Hardware
Testing High Speed Optics/Photonics
Yield Analysis and Optimization

Important Dates

Tutorial submission deadline

CLOSED

Author notification

12th May, 2026

Final manuscript due

13th June, 2026

Need Help?

For detailed information about the submission process, requirements and deadlines, the selection process and any other questions regarding the program itself or contact information, please consult the ITC India web site or email us.

Website:www.itctestweekindia.org

Program Chair Email:itc-india-tpc@googlegroups.com

Tutorial Chair Email:ITC-India-2026-Tutorials@easychair.org

ITC India invites submissions on the latest advances in test, validation and diagnosis of ICs, boards and systems.